Sotirios Ziavras
Sotirios Ziavras
Vice Provost for Graduate Studies and Dean of Graduate Faculty, Graduate Studies
353 Electrical and Computer Engineering Center (ECEC)
About Me
Dr. Ziavras received the Diploma in Electrical Engineering from the National Technical University of Athens (NTUA), Greece (1984), the M.Sc. degree in Electrical and Computer Engineering from Ohio University (1985), and the D.Sc. degree in Computer Science from George Washington University (1990).
Education
Ph.D.; George Washington University; Computer Science (Hardware And Systems ); 1990
M.S.; Ohio University; Electrical and Computing Engineering; 1985
DIPLOMA (5-year program officially but graduated in 4.5 years); National Technical University of Athens; Electrical And Computer Engineering; 1984
M.S.; Ohio University; Electrical and Computing Engineering; 1985
DIPLOMA (5-year program officially but graduated in 4.5 years); National Technical University of Athens; Electrical And Computer Engineering; 1984
Website
2024 Fall Courses
INTD 799 - RESPONSIBLE CNDCT OF RESEARCH
Teaching Interests
Advanced Computer Architecture, Embedded Computing Systems, Parallel Processing, Reconfigurable Computing,
Past Courses
ECE 394: DIGITAL SYSTEMS LAB
ECE 451: COMPUTER SYSTEMS DESIGN
ECE 452: DESIGN ADVANCS COMP ARCH
ECE 690: COMPUTER SYSTEMS ARCHITECTURE
ECE 692: EMBEDDED COMPUTING SYSTEMS
INTD 799: RESPONSIBLE CONDUCT OF RESEARCH
ECE 451: COMPUTER SYSTEMS DESIGN
ECE 452: DESIGN ADVANCS COMP ARCH
ECE 690: COMPUTER SYSTEMS ARCHITECTURE
ECE 692: EMBEDDED COMPUTING SYSTEMS
INTD 799: RESPONSIBLE CONDUCT OF RESEARCH
Research Interests
Advanced Computer Architecture, Parallel Processing, Reconfigurable Computing, Chip Multiprocessors, Embedded Computing Systems, Supercomputing, System-on-a-chip, Image processing
Journal Article
Salehin, Khondaker M, & Rojas-Cessa, Roberto, & Ziavras, Sotirios G. (2014). A Method to Measure Packet Processing Time of Hosts using High-Speed Transmission Lines. IEEE Systems Journal, PP(99), 4.
Rojas-Cessa, Roberto, & ECE, NJIT, & Ansari, Nirwan, & ECE, NJIT, & Ziavras, Sotirios G., & Khreishah, Abdallah (2013). End-to-End Network Measurement for Wired and Wireless Networks Candidate: Khondaker Musfakus Salehin Date: April 29, 2013 Time: 11: 00 AM Room: ECEC 202.
Rojas-Cessa, Roberto, & ECE, NJIT, & Ansari, Nirwan, & ECE, NJIT, & Ziavras, Sotirios G., & Khreishah, Abdallah (2013). End-to-End Network Measurement for Wired and Wireless Networks Candidate: Khondaker Musfakus Salehin Date: April 29, 2013 Time: 11: 00 AM Room: ECEC 202.
Rojas-Cessa, Roberto, & ECE, NJIT, & Ansari, Nirwan, & ECE, NJIT, & Ziavras, Sotirios G., & Khreishah, Abdallah (2013). End-to-End Network Measurement for Wired and Wireless Networks Candidate: Khondaker Musfakus Salehin Date: April 29, 2013 Time: 11: 00 AM Room: ECEC 202.
Rojas-Cessa, Roberto, & ECE, NJIT, & Ansari, Nirwan, & ECE, NJIT, & Ziavras, Sotirios G., & Khreishah, Abdallah (2013). End-to-End Network Measurement for Wired and Wireless Networks Candidate: Khondaker Musfakus Salehin Date: April 29, 2013 Time: 11: 00 AM Room: ECEC 202.
Rojas-Cessa, Roberto, & ECE, NJIT, & Ansari, Nirwan, & ECE, NJIT, & Ziavras, Sotirios G., & Khreishah, Abdallah (2013). End-to-End Network Measurement for Wired and Wireless Networks Candidate: Khondaker Musfakus Salehin Date: April 29, 2013 Time: 11: 00 AM Room: ECEC 202.
Rojas-Cessa, Roberto, & ECE, NJIT, & Ansari, Nirwan, & ECE, NJIT, & Ziavras, Sotirios G., & Khreishah, Abdallah (2013). End-to-End Network Measurement for Wired and Wireless Networks Candidate: Khondaker Musfakus Salehin Date: April 29, 2013 Time: 11: 00 AM Room: ECEC 202.
Rojas-Cessa, Roberto, & ECE, NJIT, & Ansari, Nirwan, & ECE, NJIT, & Ziavras, Sotirios G., & Khreishah, Abdallah (2013). End-to-End Network Measurement for Wired and Wireless Networks Candidate: Khondaker Musfakus Salehin Date: April 29, 2013 Time: 11: 00 AM Room: ECEC 202.
Rojas-Cessa, Roberto, & ECE, NJIT, & Ansari, Nirwan, & ECE, NJIT, & Ziavras, Sotirios G., & Khreishah, Abdallah (2013). End-to-End Network Measurement for Wired and Wireless Networks Candidate: Khondaker Musfakus Salehin Date: April 29, 2013 Time: 11: 00 AM Room: ECEC 202.
SHOW MORE
Beldianu, Spiridon Florin, & Ziavras, Sotirios G. (2013). Multicore-based Vector Coprocessor Sharing for Performance and Energy Gains. ACM Transactions on Embedded Computing Systems, 13(2), 25 pages.
Beldianu, Spiridon Florin, & Dahlberg, Christopher, & Steele, Timothy, & Ziavras, Sotirios G. (2012). Versatile Design of Shared Vector Coprocessors for Multicores. Microprocessors and Microsystems, Embedded Hardware Design, 36(7), 543–554.
Sajid, Imtiaz, & Ahmed, M M, & Ziavras, Sotirios G. (2012). Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm. Journal of Signal Processing Systems, Springer Publishers, 67(2), 157-166.
Wang, Shuai, & Hu, Jie, & Ziavras, Sotirios G. (2012). Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Transactions on Very Large Scale Integration Systems, 20(4), 643-654.
Wang, Shuai, & Hu, Jie, & Ziavras, Sotirios G. (2012). Exploring Branch Target Buffer Access Filtering for Low-Energy and High-Performance Microarchitectures. IET Computers & Digital Techniques, 6(1), 50–58.
Guinde, Nitesh B, & Ziavras, Sotirios G. (2010). Efficient Hardware Support for Pattern Matching in Network Intrusion Detection. Computers and Security/Elsevier Publishers, 29(7), 756-769.
Motahari, Sara, & Ziavras, Sotirios G., & Jones, Quentin (2010). Online Anonymity Protection in Computer-Mediated Communications. IEEE Transactions on Information Forensics & Security, 5(3), 570-580.
Beldianu, Spiridon Florin, & Rojas-Cessa, Roberto, & Oki, E, & Ziavras, Sotirios G. (2010). Scheduling for Input-Queued Packet Switches by a Re-configurable Parallel Match Evaluator. IEEE Communications Letters, 14(4), 357-359.
Beldianu, Spiridon F, & Rojas-Cessa, Roberto, & Ziavras, Sotirios G. (2010). Scheduling for Input-Queued Packet Switches by a Re-configurable Parallel Match Evaluator. IEEE Communications Letters, 14(4), 357-359.
Wang, Shuai, & Hu, Jie, & Ziavras, Sotirios G. (2009). On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Transactions on Computers (TC), 58(9), 1171 - 1184.
Beldianu, Spiridon Florin, & Dahlberg, Christopher, & Steele, Timothy, & Ziavras, Sotirios G. (2012). Versatile Design of Shared Vector Coprocessors for Multicores. Microprocessors and Microsystems, Embedded Hardware Design, 36(7), 543–554.
Sajid, Imtiaz, & Ahmed, M M, & Ziavras, Sotirios G. (2012). Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm. Journal of Signal Processing Systems, Springer Publishers, 67(2), 157-166.
Wang, Shuai, & Hu, Jie, & Ziavras, Sotirios G. (2012). Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Transactions on Very Large Scale Integration Systems, 20(4), 643-654.
Wang, Shuai, & Hu, Jie, & Ziavras, Sotirios G. (2012). Exploring Branch Target Buffer Access Filtering for Low-Energy and High-Performance Microarchitectures. IET Computers & Digital Techniques, 6(1), 50–58.
Guinde, Nitesh B, & Ziavras, Sotirios G. (2010). Efficient Hardware Support for Pattern Matching in Network Intrusion Detection. Computers and Security/Elsevier Publishers, 29(7), 756-769.
Motahari, Sara, & Ziavras, Sotirios G., & Jones, Quentin (2010). Online Anonymity Protection in Computer-Mediated Communications. IEEE Transactions on Information Forensics & Security, 5(3), 570-580.
Beldianu, Spiridon Florin, & Rojas-Cessa, Roberto, & Oki, E, & Ziavras, Sotirios G. (2010). Scheduling for Input-Queued Packet Switches by a Re-configurable Parallel Match Evaluator. IEEE Communications Letters, 14(4), 357-359.
Beldianu, Spiridon F, & Rojas-Cessa, Roberto, & Ziavras, Sotirios G. (2010). Scheduling for Input-Queued Packet Switches by a Re-configurable Parallel Match Evaluator. IEEE Communications Letters, 14(4), 357-359.
Wang, Shuai, & Hu, Jie, & Ziavras, Sotirios G. (2009). On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Transactions on Computers (TC), 58(9), 1171 - 1184.
COLLAPSE
Conference Proceeding
Efficient On-chip Vector Processing for Multicore Processors
IEEE, 15th International Symposium on System-on-Chip (SoC 2013), , October (4th Quarter/Autumn) 2013
Packet Classification using Rule Caching
IEEE International Conference on Information, Intelligence, Systems and Applications, July (3rd Quarter/Summer) 2013
FPGA and ASIC Square Root Designs for High Performance and Power Efficiency
IEEE, 24th IEEE International Conference on Application-specific Architectures and Processors (ASAP2013), June 2013
General Chairs' Message
IEEE, November 2012
On-Chip Vector Coprocessor Sharing for Multicores
19th Euromicro International Conference on Parallel, Distributed and Network-Based Computing., February 2011
IEEE, 15th International Symposium on System-on-Chip (SoC 2013), , October (4th Quarter/Autumn) 2013
Packet Classification using Rule Caching
IEEE International Conference on Information, Intelligence, Systems and Applications, July (3rd Quarter/Summer) 2013
FPGA and ASIC Square Root Designs for High Performance and Power Efficiency
IEEE, 24th IEEE International Conference on Application-specific Architectures and Processors (ASAP2013), June 2013
General Chairs' Message
IEEE, November 2012
On-Chip Vector Coprocessor Sharing for Multicores
19th Euromicro International Conference on Parallel, Distributed and Network-Based Computing., February 2011
SHOW MORE
Efficient Packet Classification on FPGAs also Targeting at Manageable Memory Consumption
International Conference on Signal Processing and Communication Systems, December 2010
Social Inference Risk Modeling in Mobile and Social Applications
Mor Naaman, Mohamed Ismail, Quentin Jones:, September 2010
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
Euromicro, September 2010
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array
Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), July (3rd Quarter/Summer) 2010
FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization
International Conference on Computer Vision Theory and Applications, , May 2010
Framework Improvement for Multi-module Embedded Reconfigurable Systems
IEEE Symposium on Field-Programmable Custom Computing Machines, May 2010
Novel FPGA-Based Signature Matching for Deep Packet Inspection
4th IFIP WG 11.2 International Workshop on Information Security Theory and Practices: Security and Privacy of Pervasive Systems and Smart Devices, April (2nd Quarter/Spring) 2010
FPGA-based Static Analysis Tool for Detecting Malicious Binaries
2nd International Conference on Computer and Automation Engineering, February 2010
Pipelined Implementation of Fixed point Square Root in FPGA Using Modified Non-Restoring Algorithm
2nd International Conference on Computer and Automation Engineering, February 2010
Preventing Unwanted Social Inferences with Classification Tree Analysis
IEEE International Conference on Tools with Artificial Intelligence, November 2009
Designing for different levels of social inference risk
Proceedings of the 5th Symposium on Usable Privacy and Security, SOUPS 2009, July (3rd Quarter/Summer) 2009
International Conference on Signal Processing and Communication Systems, December 2010
Social Inference Risk Modeling in Mobile and Social Applications
Mor Naaman, Mohamed Ismail, Quentin Jones:, September 2010
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
Euromicro, September 2010
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array
Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), July (3rd Quarter/Summer) 2010
FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization
International Conference on Computer Vision Theory and Applications, , May 2010
Framework Improvement for Multi-module Embedded Reconfigurable Systems
IEEE Symposium on Field-Programmable Custom Computing Machines, May 2010
Novel FPGA-Based Signature Matching for Deep Packet Inspection
4th IFIP WG 11.2 International Workshop on Information Security Theory and Practices: Security and Privacy of Pervasive Systems and Smart Devices, April (2nd Quarter/Spring) 2010
FPGA-based Static Analysis Tool for Detecting Malicious Binaries
2nd International Conference on Computer and Automation Engineering, February 2010
Pipelined Implementation of Fixed point Square Root in FPGA Using Modified Non-Restoring Algorithm
2nd International Conference on Computer and Automation Engineering, February 2010
Preventing Unwanted Social Inferences with Classification Tree Analysis
IEEE International Conference on Tools with Artificial Intelligence, November 2009
Designing for different levels of social inference risk
Proceedings of the 5th Symposium on Usable Privacy and Security, SOUPS 2009, July (3rd Quarter/Summer) 2009
COLLAPSE
Other
Preface and Guest Editor
International Journal on Artificial Intelligence Tools: Architectures, Languages, Algorithms, August 2010
21st IEEE International Conference on Tools with Artificial Intelligence
21st IEEE International Conference on Tools with Artificial Intelligence, November 2009
International Journal on Artificial Intelligence Tools: Architectures, Languages, Algorithms, August 2010
21st IEEE International Conference on Tools with Artificial Intelligence
21st IEEE International Conference on Tools with Artificial Intelligence, November 2009