Sotirios Ziavras

Spiridon Florin Beldianu, Sotirios G. Ziavras. 2013. “Multicore-based Vector Coprocessor Sharing for Performance and Energy Gains.” ACM Transactions on Embedded Computing Systems, vol. 13, no. 2, pp. 25 pages.

Spiridon Florin Beldianu, Christopher Dahlberg, Timothy Steele, Sotirios G. Ziavras. 2012. “Versatile Design of Shared Vector Coprocessors for Multicores.” Microprocessors and Microsystems, Embedded Hardware Design, vol. 36, no. 7, pp. 543–554.

Imtiaz Sajid, M M Ahmed, Sotirios G. Ziavras. 2012. “Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm.” Journal of Signal Processing Systems, Springer Publishers, vol. 67, no. 2, pp. 157-166.

Shuai Wang, Jie Hu, Sotirios G. Ziavras. 2012. “Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays.” IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 4, pp. 643-654.

Shuai Wang, Jie Hu, Sotirios G. Ziavras. 2012. “Exploring Branch Target Buffer Access Filtering for Low-Energy and High-Performance Microarchitectures.” IET Computers & Digital Techniques, vol. 6, no. 1, pp. 50–58.

Nitesh B Guinde, Sotirios G. Ziavras. 2010. “Efficient Hardware Support for Pattern Matching in Network Intrusion Detection.” Computers and Security/Elsevier Publishers, vol. 29, no. 7, pp. 756-769.

Sara Motahari, Sotirios G. Ziavras, Quentin Jones. 2010. “Online Anonymity Protection in Computer-Mediated Communications.” IEEE Transactions on Information Forensics & Security, vol. 5, no. 3, pp. 570-580.

Spiridon Florin Beldianu, Roberto Rojas-Cessa, E Oki, Sotirios G. Ziavras. 2010. “Scheduling for Input-Queued Packet Switches by a Re-configurable Parallel Match Evaluator.” IEEE Communications Letters, vol. 14, no. 4, pp. 357-359.

Spiridon F Beldianu, Roberto Rojas-Cessa, Sotirios G. Ziavras. 2010. “Scheduling for Input-Queued Packet Switches by a Re-configurable Parallel Match Evaluator.” IEEE Communications Letters, vol. 14, no. 4, pp. 357-359.

Shuai Wang, Jie Hu, Sotirios G. Ziavras. 2009. “On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors.” IEEE Transactions on Computers (TC), vol. 58, no. 9, pp. 1171 - 1184.

“Efficient Packet Classification on FPGAs also Targeting at Manageable Memory Consumption”
International Conference on Signal Processing and Communication Systems, December 2010.

“Social Inference Risk Modeling in Mobile and Social Applications”
Mor Naaman, Mohamed Ismail, Quentin Jones:, September 2010.

“Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance”
Euromicro, September 2010.

“TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array”
Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), July (3rd Quarter/Summer) 2010.

“FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization”
International Conference on Computer Vision Theory and Applications, , May 2010.

“Framework Improvement for Multi-module Embedded Reconfigurable Systems”
IEEE Symposium on Field-Programmable Custom Computing Machines, May 2010.

“Novel FPGA-Based Signature Matching for Deep Packet Inspection”
4th IFIP WG 11.2 International Workshop on Information Security Theory and Practices: Security and Privacy of Pervasive Systems and Smart Devices, April (2nd Quarter/Spring) 2010.

“FPGA-based Static Analysis Tool for Detecting Malicious Binaries”
2nd International Conference on Computer and Automation Engineering, February 2010.

“Pipelined Implementation of Fixed point Square Root in FPGA Using Modified Non-Restoring Algorithm”
2nd International Conference on Computer and Automation Engineering, February 2010.

“Preventing Unwanted Social Inferences with Classification Tree Analysis”
IEEE International Conference on Tools with Artificial Intelligence, November 2009.

“Designing for different levels of social inference risk”
Proceedings of the 5th Symposium on Usable Privacy and Security, SOUPS 2009, July (3rd Quarter/Summer) 2009.